In an integrated circuit, many different electronic devices or components such as transistors or capacitances are formed in or on a specific substrate which generally has a planar configuration. The electrical connections between these electronic devices located on a substrate occurs through a network of metal interconnects or interconnections. Nowadays, complex integrated circuits are formed with different metal layers or levels. The network of interconnects may include:    inner-level connections also called metal lines which make connections in the same layer;    inter-level connections called vias, which, are metal links which connect consecutive metals layers.
Metal lines and vias represent metallization layers also called interconnections or interconnects of an integrated circuit. Interconnections may be made of copper or aluminium or any other conducting material. Most recent integrated circuits use copper as the interconnection material as copper has a better electrical conductivity and a better electromigration resistance than aluminium.
Interconnects comprises a liner and a capping layer. For copper interconnects, the liner or the metal line of the interconnect is made of a tantalum material and surrounds the bottom and lateral surface of the interconnect in order to act as a copper diffusion barrier with the rest of the circuit. The capping layer is made of a silicon nitride material. The capping layer may also act as a diffusion barrier and a via etch stop layer. All interconnects are surrounded by dielectric materials to electrically insulate them from any other circuit.
Generally, recent integrated circuits use a dielectric layer which comprises a low-k dielectric. This low-k dielectric is a low permittivity material but moreover, it presents a low mechanical resistance.
As the number of electronic component on an integrated circuit continues to increase, the number of electrical interconnections is also growing significantly. The high number of electrical interconnections in a circuit and the reduction of device dimensions lead to many reliability issues. One of these reliability issues is electromigration concerns in a metal interconnect. When a current is flowing in the circuit, this current flow provides an electric potential in the interconnections. Due to this electrical potential, one portion of the interconnect structure becomes a cathode and the other portion becomes an anode.
As electrons always flow in an opposite direction from the direction of the current, electrons flow from the cathode to the anode. Such a movement of electrons generates movement of atoms of copper because electrons collide with atoms of copper in the copper interconnections. The atoms of copper tend to migrate in the same direction as the flow of electrons. Thus atoms of copper move to the anode side of the interconnection. Such an atoms movement is called electromigration flow. The liner edge of the liner above mentioned prevents atoms of copper reaching the dielectric layer and passing to the other metal levels through the vias. The cumulation of atoms of copper generates a compression state in the interconnect with respect to the dielectric environment at one side of the interconnect. This compression force applies to both the liner and the dielectric layer. Consequently, there is a mechanical stress gradient present along the interconnect. This stress gradient tends to create an opposite force in order to counter balance the electromigration flow: this is the well known Blech effect.
The opposite force tends to push back the atoms of copper to the cathode, against the electromigration force. This opposite force is linked to the mechanical resistance of the low k dielectric.
However the opposite force never compensates enough for the electromigration force. Thus electromigration phenomenon causes interconnect failure and consequently integrated circuits dysfunction which can lead to short circuits in the integrated circuit.
In certain prior art structure, one or more dummy copper cubes may be found interspersed over the layers in order to bring about a level of homogeneous density to the finished integrated circuit or device. The dummy cubes are randomly disposed, the aim of such an arrangement is to obtain an homogeneous density of all the elements on the integrated circuit or device.